TSHFD=0, TFDIR=0, TFSI=0, TFSL=0, TEFS=0, TSCKP=0, TXBIT0=0, TFEN0=0, TXDIR=0, TFEN1=0
I2S Transmit Configuration Register
| TEFS | Transmit Early Frame Sync. 0 (0): Transmit frame sync initiated as the first bit of data is transmitted. 1 (1): Transmit frame sync is initiated one bit before the data is transmitted. |
| TFSL | Transmit Frame Sync Length. 0 (0): Transmit frame sync is one-word long. 1 (1): Transmit frame sync is one-clock-bit long. |
| TFSI | Transmit Frame Sync Invert. 0 (0): Transmit frame sync is active high. 1 (1): Transmit frame sync is active low. |
| TSCKP | Transmit Clock Polarity. 0 (0): Data clocked out on rising edge of bit clock. 1 (1): Data clocked out on falling edge of bit clock. |
| TSHFD | Transmit Shift Direction. 0 (0): Data transmitted MSB first. 1 (1): Data transmitted LSB first. |
| TXDIR | Transmit clock direction 0 (0): Transmit clock is external. 1 (1): Transmit clock generated internally |
| TFDIR | Transmit Frame Direction. 0 (0): Frame sync is external. 1 (1): Frame sync generated internally. |
| TFEN0 | Transmit FIFO Enable 0. 0 (0): Transmit FIFO 0 disabled. 1 (1): Transmit FIFO 0 enabled. |
| TFEN1 | Transmit FIFO Enable 1. 0 (0): Transmit FIFO 1 disabled. 1 (1): Transmit FIFO 1 enabled. |
| TXBIT0 | Transmit Bit 0. 0 (0): Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of transmit shift register (MSB aligned). 1 (1): Shifting with respect to bit 0 of transmit shift register (LSB aligned). |